1. Field of the Invention
The present invention relates to a multi-port semiconductor memory, or a semiconductor memory having multiple input and output ports.
2. Description of the Related Art
The multi-port semiconductor memory has been used for, for example, a register file for microprocessor or image memory for graphics. Each of the multiple ports of the multi-port semiconductor memory can perform write-in or read-out of data independently. That is, input and output of data through respective input and output ports are performed concurrently. Therefore, since waiting time for the input and output of data is reduced, processing capacity of the processor is improved as a whole. For example, in a microprocessor using a two-port semiconductor memory, two data can be loaded in one cycle.
As the literatures regarding the multi-port semiconductor memory, for example, JP-A-07-230692, JP-A-09-7373, and JP-A-11-261017 are known, of which the contents are incorporated herein by reference.
Typically, in the two-port semiconductor memory, one memory cell is connected to two sets of bit line pairs. For example, in the two-port semiconductor memory described in FIG. 3 in the above JP-A-09-7373, one memory cell 11 is connected to a bit line pair WBL, WBL/ and a bit line pair RBL, RBL/.
In such configured memory, coupling capacitance is produced between adjacent bit lines. For example, in the two-port semiconductor memory described in FIG. 3 in JP-A-9-7373, the coupling capacitance is produced between the bit lines WBL and RBL, in addition, the coupling capacitance is produced between the bit lines WBL/ and RBL/. The coupling capacitance is a cause of coupling noise. For example, if electrical potential of the bit line RBL is changed from high-level to low-level while the bit line WBL is being on high level, electrical potential of the bit line WBL is temporarily dropped. If the electrical potential of the bit line WBL is read out while the coupling noise is being generated, the read-out data value may be wrong.
The coupling noise disappears after a certain period of time has passed since the noise was generated. Therefore, if it is determined that the electrical potential of one of the bit line pairs must not be read out before the predetermined time has passed since the electrical potential of the other of the bit line pairs was changed, the wrong read-out can be prevented. That is, influence of the coupling noise can be eliminated by staggering the read-out timing from the write-in timing.
Here, when the coupling capacitance is small, since generating time of the coupling noise is short, the wrong read-out can be prevented only by staggering the read-out from the write-in for a short time. On the other hand, when the coupling capacitance is large, the generating time of the coupling noise is long, therefore the read-out time of the two-port semiconductor memory is substantially lengthened. Today, distance among the bit lines is apt to be shortened with progress of fining of an integrated circuit, furthermore, bit line length is apt to be elongated according to increase of memory capacity. Each of them is a factor for increasing the coupling capacitance, or factor for lengthening the generating time of the coupling noise. Therefore, the read-out time becomes substantially longer as the fining of memory and increase of the memory capacity are progressed.
The subject of the invention is to provide a multi-port semiconductor memory in which the wrong read-out due to the coupling noise is hardly generated and operation speed is substantially fast.